Domain depth, sharpened by AI.
Fifteen years turning fab data into working products. Now building the AI tools engineers actually use.
- Now
- Principal Engineer, Silicon Photonics Process, Nokia Singapore, from Oct'26.
- Before
- HP, CompoundTek, STMicroelectronics, GlobalFoundries.
- Studying
- Master of Computing (Artificial Intelligence), NUS. Part-time, to Dec'27.
- Built
- Quinn, an on-premises LLM agent platform for fab data.
- 15years in semiconductors
- 8provisional patents, silicon photonics
- +1 qtrproduction start pulled in, BCD transfer
- $1M/yrcost reduction delivered, FY26
Both sides of the foundry relationship
Customer side at HP and STMicroelectronics. Foundry side at CompoundTek and GlobalFoundries. All in Singapore.
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Principal Engineer, Silicon Photonics Process
Process integration, NPI and the foundry interface for silicon photonics platforms.
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Product Engineering Expert
- Led new product development for HP's next-generation silicon printhead platform. Foundry interface for NPI and R&D projects.
- Qualified HP's Southeast Asia wafer and packaging fabs for new products.
- Cost reduction programs: $1M/yr savings in FY26 from die shrink, mask layer and process step elimination.
- Initiated and led Quinn, the AI platform for manufacturing data analysis.
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Technology & Program Manager
A 200mm silicon photonics pure-play foundry.
- Owned the technology roadmap and the process design kit (PDK).
- Drove customer programs from first silicon to production release. Half the client base production-ready within 1yr.
- Designed devices and test structures for process monitoring. Filed 8 provisional patent applications.
- Partnered with EDA vendors on the PDK and on joint demos: OFC 2020, Cadence CONNECT, an Ansys webinar.
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Program Management Engineer
- Supervised advanced BCD technology transfer to the Singapore fab: toolset comparison, recipe matching, short loops, swap lots, qualification.
- Parametric and yield parity with the sister fab in the first learning cycle. --> Production start pulled in by 1 quarter.
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Senior Process Integration Engineer
- Led the 200mm silicon photonics program on an integration scheme distinct from the CMOS baseline. Production readiness for half the customer base within 1yr.
- Took 0.16um BCD from qualification to risk production at thousands of wafer starts a week, with yield above the mother fab.
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General Manager, Vietnam
- Opened the Vietnam market for an MES and industrial IoT company: reseller network, government and university outreach, a smart manufacturing whitepaper.
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PhD candidate, RFIC design
- Nanyang President's Graduate Scholarship. Taped out a UWB low-noise amplifier on 65nm CMOS. Teaching assistant for 6 semesters.
- Left without the degree to take the Arcstone role.
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Process Integration Engineer
- Process qualification for new and transferred projects: 0.35um SiGe BiCMOS, 0.35um EEPROM, 0.18um high-voltage. 3 internal awards in 2yrs.
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Founder
- Pressure mapping for knee replacement surgery, with Singapore General Hospital. Finalist, Lee Kuan Yew Global Business Plan Competition.
An on-premises LLM agent platform for fab data
Quinn is a chat assistant for semiconductor manufacturing data. Built at HP with the product and process engineers who use it. Pilot in Sep'26.
An engineer asks in plain words. Quinn finds the lots, pulls lot history, electrical test, metrology and inspection data, maps pedigree across wafer, module and assembly segments, runs the analysis and renders the maps.
Deterministic spine, intelligence at the edges
- The model routes the turn and writes the summary. It sees a tool catalog and compact result summaries, never the full data.
- Every tool call is schema-checked before it runs. SQL, statistics and plots are deterministic code.
- Open-weight models served on the fab network. Nothing leaves the site.
- A turn that fails after tools have run returns a partial envelope. --> Completed analysis is never discarded.
# Things engineers ask Quinn
Get 10 production lots from Jul'25
Extract lot history for [lot]
Calculate yield and pareto
Plot [parameter] by panel id
Tool commonality: GOOD [lots], BAD [lots]
Localise [bin] for [lot]
- Agents
- 21 agents, about 50 tools. Extraction, analysis, visualisation, tool commonality, split analysis, lot and spatial localisation, cross-segment pedigree, yield reports.
- Statistics
- Fisher's exact test with Benjamini-Hochberg FDR for tool commonality. Welch's t and random-effects log-odds for process splits. Excess-mass origin verdicts for localisation.
- Stack
- Python, Streamlit, DuckDB mirror, Chroma for RAG, Ollama for local serving, a vision model for inspection images. Multi-agent tool dispatch on the Model Context Protocol (MCP).
- Output
- Tables, wafer and panel maps, Pareto and control charts, PowerPoint reports, scheduled yield monitoring.
What I work with
CMOS (BCD), MEMS and silicon photonics processes and devices. Technology transfer end to end: unit-process matching, parametric alignment, reliability qualification, early production ramp. SPC, DOE, process change management, tapeout flow, DRC.
Inline, parametric, electrical test, sort and final test. Yield, defect and tool commonality analysis. JMP with JSL, Excel with VBA, Klarity Defect, SQL.
Python with pandas, NumPy, SciPy, scikit-learn, PyTorch. RAG, agentic tool use, multi-agent systems, local LLM serving. Bayesian networks, HMMs, MCMC, variational inference. CNNs, transformers. Spark.
KLayout with Ruby and Python scripting (cross-sections generated from GDS), Mentor Calibre DRC, Tanner L-Edit, Lumerical, Cadence, HFSS, ADS.
Customer programs from first silicon to production release. NPI across foundry, wafer fab and packaging. Cost reduction and process simplification.
Vietnamese (native), English (fluent).
NUS and NTU
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Master of Computing, Artificial Intelligence
- Part-time, alongside work. Courses chosen for fab and design data: Neural Networks and Deep Learning, Knowledge Discovery and Data Mining, Uncertainty Modelling in AI, Big Data Systems for Data Science, Graph Machine Learning.
- Projects: HDB resale price prediction on 212k transactions with stacked gradient-boosted models, 6th on the public leaderboard. Image classification attribution study on Mini-ImageNet across 5 CNN backbones.
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BEng, Electrical and Electronic Engineering
- First Class Honours. Dean's List. Specialisation in microelectronics, minor in entrepreneurship. Exchange semester at Monash University.
Based in Singapore since 2006
I'm David. Vietnamese, educated at NTU, 15yrs in Singapore fabs and foundries.
I started in process integration, moved to technology transfer, ran the roadmap and PDK at a photonics foundry, then spent 5yrs in product engineering at HP. From Oct'26 I'm at Nokia on silicon photonics process.
The AI work grew out of the day job. Root-cause work on fab data is repetitive: find the lots, pull the data, join the segments, run the same statistics. Quinn turns that into a conversation. The NUS master's runs alongside it, part-time, to put theory under what I had already built.
Side tracks: two VC internships, two startups, 6 semesters of teaching.
- Tennis most weeks.
- Beyblade X with my son. Tournament data over reviewer opinion.
- A home lab on Proxmox. Emma, my own assistant, runs there and answers on Discord and Telegram.
- Notes in Obsidian. One fact per file, dated YYMMDD.
Email works best
Happy to talk about silicon photonics process, fab data and AI tooling.
- david@davidngo.com
- linkedin.com/in/ngothanhtrung
- GitHub
- github.com/davidngo256
- Location
- Singapore
- CV
- This page prints cleanly. A PDF on request.